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Espressif Systems /ESP32-P4 /CACHE /L1_CACHE_WRAP_AROUND_CTRL

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Interpret as L1_CACHE_WRAP_AROUND_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L1_ICACHE0_WRAP)L1_ICACHE0_WRAP 0 (L1_ICACHE1_WRAP)L1_ICACHE1_WRAP 0 (L1_ICACHE2_WRAP)L1_ICACHE2_WRAP 0 (L1_ICACHE3_WRAP)L1_ICACHE3_WRAP 0 (L1_DCACHE_WRAP)L1_DCACHE_WRAP

Description

Cache wrap around control register

Fields

L1_ICACHE0_WRAP

Set this bit as 1 to enable L1-ICache0 wrap around mode.
L1_ICACHE1_WRAP

Set this bit as 1 to enable L1-ICache1 wrap around mode.
L1_ICACHE2_WRAP

Reserved
L1_ICACHE3_WRAP

Reserved
L1_DCACHE_WRAP

Set this bit as 1 to enable L1-DCache wrap around mode.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd